ICS8430S07AKILF【PDF 1/26 页】IC CLK GENERATOR PLL 32VFQFN

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DATA SHEET

ICS8430S07AKI REVISION A SEPTEMBER 3, 2009

2009 Integrated Device Technology, Inc.

Clock Generator for Cavium Processors

ICS8430S07I

General Description

The ICS8430S07I is a PLL-based clock generator

specifically designed for Cavium Networks SoC

processors. This high performance device is optimized

to generate the processor core reference clock, the

DDR reference clocks, the PCI/PCI-X bus clocks, and

the clocks for both the Gigabit Ethernet MAC and PHY. The clock

generator offers ultra low-jitter, low-skew clock outputs, and edge

rates that easily meet the input requirements for the

CN3005/CN3010/CN3020 processors. The output frequencies are

generated from a 25MHz external input source or an external 25MHz

parallel resonant crystal. The extended temperature range of the

ICS8430S07I supports telecommunication, networking, and storage

requirements.

Applications

Systems using CN30XX MIPS64 Broadband Processors

Networking, control and storage equipment, including routers,

switches, application-aware gateways, triple-play gateways,

WLAN and 3G/4G access and aggregation devices, storage

arrays, storage networking equipment, servers, and intelligent

NICs

802.11 a/b/g/n wireless for home data and multi-media distribution

QoS for high quality Voice, Video, and Data Service

Next-generation PON, VDSL2, and Cable Networks

High-performance NAS

Audio/Video Storage and Distribution

Consumer Space Media Server

Features

One selectable differential LVPECL output pair for DDR

533/400/667

Six LVCMOS/ LVTTL outputs, 15 typical output impedance

- One selectable core clock for the processor

- One selectable clock for the PCI/ PCI-X bus

- One 125MHz clock reference for GbE MAC

- Three 25MHz clock references for GbE PHY

Selectable external crystal or differential (single-ended) input

source

Crystal oscillator interface designed for 25MHz, parallel resonant

crystal

Differential input pair (CLK, nCLK) accepts LVPECL, LVDS,

LVHSTL, SSTL, HCSL input levels

Internal resistor bias on nCLK pin allows the user to drive CLK

input with external single-ended (LVCMOS/ LVTTL) input levels

RMS phase jitter @ 125MHz, using a 25MHz crystal

(1.875MHz - 20MHz): 0.78ps (typical), QD output

Output supply:

LVPECL – 3.3V Core

LVCMOS – Core/Output

3.3V/3.3V

3.3V/2.5V

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) package

HiPerClockS

ICS

Pin Assignment

910 11 12 13 14 15 16

32 31 30 29 28 27 26 25

VDD

nPLL_SEL

XTAL_IN

XTAL_ OUT

nXTAL_SEL

CLK

nCLK

GND

VDDO_B

VDDO_C

MR/ nOE_REF

CORE_SEL

SEL

O_R

DDO_D

ICS8430S07I

32-Lead VFQFN

5mm x 5mm x 0.925mm

package body

K Package

Top View

O_R

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